1. Field of the Invention
This invention relates to a method for forming a flash memory device containing dielectric layers between a floating gate and a control gate, and more particularly to a method for forming a floating gate of the flash memory device without the loss of capability of storing charges.
2. Description of the Prior Art
Generally, a stacked gate of a flash memory device is formed by performing the steps of: forming a field oxide layer, a gate oxide, a polysilicon layer for a floating gate, a dielectric layer and a polysilicon layer for a control gate are formed, in order, on a silicon substrate; forming the polysilicon layer for the control gate; the dielectric layer and the polysilicon layer for the floating gate are selectively etched, so that the stacked gate pattern is formed. Herein, the dielectric layer is composed of a stacked layer including, a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
However, in the dry etching process for forming the stacked gate pattern, the substrate is damaged, so that the characteristics of the device are degraded.
A conventional method for forming a stacked gate of a flash memory device in order to solve the above mentioned problem is shown in FIGS. 1A to 1C.
First, referring to FIG. 1A, field oxide layers 12 are formed on a silicon substrate 11 by the thermal oxidation process and then a gate oxide layer 13 is formed. A polysilicon layer 14 for a floating gate is deposited on top of the gate oxide layer 13, and a silicon oxide layer 15 and a silicon nitride layer 16 are formed one by one on the polysilicon layer 14. A photoresist pattern 17, which is to be used as a mask of ion implanting and etching, is formed on the silicon nitride layer 16.
Referring next to FIG. 1B, the silicon nitride layer 16, the silicon oxide layer 15 and the polysilicon layer 14 are selectively etched, in order, using the photoresist patter 17 as an etching mask. N-type impurities, such as arsentc ions, are implanted into the silicon substrate 11, which is exposed by the anisotropic dry etching, to form source/drain regions(not shown) using the photoresist pattern 17 as an ion implantation mask.
Referring next to FIG. 1C, a silicon oxide layer 18 is formed on the silicon nitride layer 16 by the thermal oxidation process after removing the photoresist pattern 17. The silicon oxide layer, 18 can be replaced by an oxide layer which is formed in a high temperature atmosphere. A polysilicon layer 19 for a control gate is formed over the entire structure and a photoresist pattern 20 is formed to pattern a control gate. In the process of forming the silicon oxide layer 18, the exposed silicon substrate is also oxidized to form a silicon oxide layer 18', which is thicker than the silicon oxide layer 18 formed on the silicon nitride layer 16. Therefore, the silicon oxide layer 18' prevents the silicon substrate 11 from being damaged in the following dry etching process for forming the control gate pattern. On the other hand, the exposed sidewalls of the polysilicon layer 14 are also oxidized rapidly, so that an oxidized area 14' is formed in a part of the floating gate. As a result, the width of the floating gate is smaller than the desired width "A" by the width of the oxidized area 14'.